Rate Optimal VLSI Design from Data Flow Graph
نویسندگان
چکیده
This paper considers the rate optimal VLSI design of a recursive data ow graph (DFG). Previous research on rate optimal scheduling is not directly applicable to VLSI design. We propose a technique that inserts bu er registers to allow overlapped rate optimal implementation of VLSI. We illustrate that nonoverlapped schedules can be implemented by a simpler control path but with a larger unfolding factor, if exists, than overlapped schedules.
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